Many computers and calculators have requirements for registers wherein the binary contents can be incremented or decremented by 1. Such registers are known as half-adders. The speed of a binary half-adder is limited, in part, by the speed at which any carry bit resulting from the summation of the binary content of a logic cell and the carry bit input to such logic cell can be propagated to the sequent more significant bit logic cell. Prior art binary half-adders are disadvantageous in that the carry bit from a less significant bit within the half-adder cannot be propagated to the next more significant bit until summation calculations for the less significant digit have been completed.
A full-adder, i.e. a register whose binary contents can be summed with the contents of a second register, which employs separate summing and carry circuitry is disclosed in a co-pending Patent Application entitled BINARY ADDER, Ser. No. 650,211 filed Jan. 19, 1976 by David Steven Maitland and Billy E. Thayer. However, the use of a full-adder for a special half-adder application is wasteful of speed, power and space, and a specialized and simplified half-adder is desired.
Accordingly, it is the principal object of this invention to provide a modular binary half-adder having the capability of propagating carry bit signals prior to the modification of the register content.
It is a further object of this invention to provide a modular binary half-adder having the capability of updating all of the bits in a binary register in one parallel operation subsequent to the propagation of the carry bit signals.
This and other objects have been accomplished in accordance with the preferred embodiment of the invention by the use of a modular binary half-adder having separate summing and carry circuitry. The status of the output carry signal from any logic cell is precalculated as a function of an input carry signal and the contents of the associated storage element. Subsequently, the summation operations are carried out upon all the storage elements in one parallel operation in response to the preset carry signals and the contents of the associated storage elements.